PCI-SIG, the consortium that governs the PCI Express I/O interconnect, released draft specification version 0.7 for the upcoming PCI-Express 7.0 standard (or PCIe Gen 7). An early-2025 release of this draft could indicate that PCIe Gen 7 gets finalized into specification version 1.0 by the end of 2025, from where implementers can pick it up to design their devices around. We are now at 32 Gbps per lane per direction with PCIe Gen 5, and PCIe Gen 6 doubles it to 64 Gbps, which would mean PCIe Gen 7 will double that further to 128 Gbps per lane per direction. PCI-Express 7.0 x1 would offer the same bandwidth as PCI-Express 3.0 x16. We could realistically expect the first computing platforms implementing PCIe Gen 7 to come out around 2027 or even 2028. PCIe forms the physical layer for a number of derivative standards, such as CXL, Thunderbolt, USB (USB 3.0 onwards), NVMe, SDexpress, CFexpress, and DMI.Many Thanks to Tumble George for the tip

PCI-SIG today announced that the PCI Express (PCIe ) 7.0 specification will double the data rate to 128 GT/s and is targeted for release to members in 2025. "For 30 years the guiding principle of PCI-SIG has been, 'If we build it, they will come,'" observed Nathan Brookwood, Research Fellow at Insight 64. "Early parallel versions of PCI technology accommodated speeds of hundreds of megabytes/second, well matched to the graphics, storage and networking demands of the 1990s.

In 2003, PCI-SIG evolved to a serial design that supported speeds of gigabytes/second to accommodate faster solid-state disks and 100MbE Ethernet. Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. Today's announcement of PCI-SIG's plan to double the channel's speed to 512 GB/s (bi-directionally) puts it on track to double PCIe specification performance for another 3-year cycle."